Clock Generation and Reset Control Registers
15-50
15.4 Clock Generation and Reset Control Registers
The clock generation and system reset module contains 16-bit registers for the
following functions:
-
Reset control
-
System clocks
-
Power-saving mode
-
Wake-up control
-
Operations
-
CLKOUT pins
These registers are partitioned into MPU (see Table 15–5) and DSP (see
Table 15–17) groups.
Note:
All MPU clock generator and system reset control registers are 32-bit ac-
cessed and all are 32-bit word aligned. All DSP control registers are 16-bit
accessed by the DSP and 32-bit word aligned.
-
The MPU address for these registers starts at address(hex): FFFFCE80.
Note:
All registers dedicated to the MPU are write-accessed in supervisor mode
only.
-
Some registers
are dedicated to the DSP subsystem and can be moni-
tored by the DSP only. Those registers are mapped to the DSP memory
space starting at DSP word address (hex): 004000. They can also be
accessed by the MPU through the MPUI interface.
The remaining registers
are controlled by the MPU only. They are memory
mapped to the MPU memory space starting at address (hex): FFFECE00.
The physical address of a register is the starting address (defined by the
system) plus the offset address (given in Table 15–5 and following registers).
Each processor can read its associated registers at any time without affecting
ongoing operations, and the registers can be written via their bits.
Table 15–5 lists the MPU clock/reset/power mode control registers.
Bit Width: 32
In the OMAP5910 device, the MPU is the master at all times; it has complete
control of the clock generator and system reset module.
