Traffic Controller Memory Interface Registers
4-51
Memory Interface Traffic Controller
Table 4–19. SDRAM Timing Requirements
ac Parameters
SDRAM Timing
Requirements (ns)
Meeting this Timing
With SDRAM.CLK =
60 MHz (16.7 ns
Period)
t
rc
80
5
t
ras
48
3
t
rp
24
2
t
rcd
24
2
t
rrd
{
16
1
t
dpl
(trwl)
}
8
–
t
dal
27
–
t
rsc
2
1
† Write is never interrupted by precharge command directly.
‡ Neither read or write with autoprecharge is supported.
For 60 MHz, timing can be met by using the SDF1 timing configuration.
This register, when written, programs the SDRAM MRS (default) and EMRS
configuration registers. In default mode, a write to the register initiates an MRS
request to the SDRAM. In EMRS mode, a write to this same register initiates
an EMRS request. Reading this register does not issue an external transac-
tion. Table 4–20 describes the bits for the MRS mode. Table 4–21 describes
the bits for the EMRS mode.
