UART FIFO Configuration
12-102
12.12 UART FIFO Configuration
The goal of the UART FIFO configuration is to set trigger level for halt/restore
(TCR register), set trigger level for transmit/receive (TLR register), and
configure the FIFO (FCR register).
The procedure of the UART FIFO configuration is as follows:
1) Write into both the TLR and TCR registers
J
Set EFR[4] to 1
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Set MCR[6] to 1.
2) Write into FCR.
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Set EFR[4] to 1.
EFR[4] = 1 has already been done in the previous section, so a simple
write to MCR[6] is necessary.
3) Set TCR TLR and FCR to the desired value.
Here accesses to TCR TLR and FCR must be disabled to avoid any further
undesired write to these registers:
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LCR=0xBF (provides access to EFR)
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EFR[4]=0
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LCR[7]=0
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MCR[6]=0
12.12.1
Baud Rate Data and Stop Configuration
The goals of the baud rate and stop configuration are to configure UART data,
stop (LCR register) baud rate (DLH and DLL registers), and enable UART
operation. If interrupt capability is added, configuration must be added right
before UART enable.
The procedure to accomplish these goals is as follows:
1) Input clock is 12 MHz, so set OSC_12M_SEL to 1.
2) Set LCR to desired value.
3) LCR[7] to 1 (access to DLH and DLL registers).
4) Set DLH and DLL.
5) LCR[7]=0 (removes access to DLH and DLL registers)
6) Set IER to desired value (sets interrupts).
7) MDR1[2:0]=0 (enables UART)
The UART module is operational.
