MMC/SD Host Controller
7-154
Clock Phase (PHA)
The clock polarity and clock phase bits select four different clocking schemes
for the SPICLK pin.
The clock phase bit (1) selects a half cycle delay for clock.
When clock phase = 0:
-
MSB data is ready one half cycle of SPICLK before the SPI clock starts.
-
Data is shifted-in in reception on the first edge transition of SPICLK.
-
Data is shifted-out in transmission on the second edge transition of
SPICLK.
When clock phase = 1:
-
Data is shifted-out in transmission on the first edge transition of SPICLK.
Data is shifted-in in reception on the second edge transition of SPICLK:
J
0: Phase 0
J
1: Phase 1
Value after reset is low.
Clock Polarity (POL)
The clock polarity bit (0) selects the active edge of the clock, either rising or
falling.
When 0, the idle value of the SPI clock signal is low and the rising edge is
active.
When 1, the idle value of the SPI clock signal is high and the falling edge is
active.
-
0: Rising edge active
-
1: Falling edge active
Value after reset is low.
