UART/IrDA Control and Status Registers
12-61
UART Devices
Table 12–50. UART Mode Line Status Register (UART_LSR) (Continued)
Bit
Reset
Value
R/W
Function
Value
Name
3
RX_FE
0
No framing error in data being read from
RX FIFO
R
0
1
Framing error occurred in data being read
from RX FIFO (received data did not have a
valid stop bit).
2
RX_PE
0
No parity error in data being read from RX
FIFO
R
0
1
Parity error in data being read from RX
FIFO
1
RX_OE
0
No overrun error
R
0
1
Overrun error has occurred. Set when the
character held in the receive shift register is
not transferred to the RX FIFO. This case
can occur only when the receive FIFO is
full.
0
RX_FIFO_E
0
No data in the receive FIFO
R
0
1
At least one data character in the RX_FIFO
When the line status register (LSR) is read, LSR[4:2] reflect the error bits (BI,
FE, PE) of the character at the top of the RX FIFO (next character to be read).
Therefore, reading the LSR and then reading the RHR identifies errors in a
character.
LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared
only when there are no more errors remaining in the FIFO.
Reading the LSR does not cause an increment of the RX FIFO read pointer.
The RX FIFO read pointer is incremented by reading the RHR.
