LCD Controller Registers
11-23
LCD Controller
11.8 LCD Controller Registers
The LCD controller contains four control registers and one status register.
The control registers contain bit fields to enable and disable the LCD controller
to define:
-
The height and width of the screen being controlled
-
Color or monochrome mode
-
Passive or active display
-
Polarity of the control lines
-
Pulse width of the line and frame clocks
-
The pixel clock and ac-bias frequency
-
The number of delays to insert before/after each line and after each frame
An additional control field exists to tune the DMA performance, based on the
type of memory system in which the LCD controller is used. This field controls
the placement of a minimum delay between each LCD palette request to
ensure enough bus bandwidth is given to other systems access. This field is
only used for palette load.
The status register contains bits that signal:
-
FIFO underrun error
-
Frame synchronization error
-
When the last active frame has completed after the LCD is disabled
(maskable)
-
ac counter, if programmed
Each of these hardware-detected events signals an interrupt request to the
interrupt controller.
Table 11–10 lists the LCD controller registers. Table
11–11 through
Table 11–23 describe the register bits.
Table 11–10. LCD Controller Registers
Register
Description
R/W
Size
Address
LcdControl
LCD control
R/W
32 bits
FFFE:C000
LcdTiming0
LCD timing 0
R/W
32 bits
FFFE:C004
LcdTiming1
LCD timing 1
R/W
32 bits
FFFE:C008
LcdTiming2
LCD timing 2
R/W
32 bits
FFFE:C00C
LcdStatus
LCD status
R/W
32 bits
FFFE:C010
LcdSubpanel
LCD subpanel display
R/W
32 bits
FFFE:C014
