MPU Memory Management Unit
2-34
2.7.6.4
Translating Section References
Figure 2–14 illustrates the complete section translation sequence. The access
permissions contained in the level 1 descriptor must be checked before the
physical address is put on the address bus.
Figure 2–14. Section Translation
31
20 19
18
12
14 13
2 1
0
0
0
Virtual address
Table index
Section index
Translation base
Translation table base
First-level descriptor
Table index
Translation base
31
31
31
0
0
0
14 13
Physical address
Section index
AP
C B
Domain 1
1 0
Section base address
Section base address
12
31
0
9 8
5 4 3 2 1
20 19
12 11 10
12
20 19