Clock Generation and Reset Control Registers
15-57
Clock Generation and System Reset Management
The MPU idle mode entry 2 register (ARM_IDLECT2) controls the clock
domains independently of the MPU state.
Table 15–11. MPU Idle Mode Entry 2 Register (ARM_IDLECT2)
Bit
Name
Value
Description
Type
Reset
Value
15–11 RESERVED
Reading these bits gives undefined values. Writing
to them has no effect.
0x08
10
RESERVED
Reserved. This bit should always be written as 0.
R/W
0
9
EN_ GPIOCK
Enables clock of MPU GPIO connected to MPU
TIPB:
R/W
0
0
MPU GPIO clock stopped—bit must be set to logic
1 to enable clock activity
1
MPU GPIO clock active
8
DMACK_REQ
Disables permanently-supplied-clock to system
DMA controller to function on a clock request basis:
R/W
1
0
DMA clock shutdown when idle mode is entered if
IDLIF_ARM = 1
1
DMA clock stopped by default (reactivated upon
DMA requests only)
7
EN_ TIMCK
Enables clock of MPU timer connected to MPU
TIPB:
R/W
0
0
MPU timer clock is stopped—bit must be set to
logic 1 to enable clock activity
1
MPU timer clock active and can be stopped
depending on IDLTIM_ARM bit of MPU idle mode
entry 1 register (ARM_IDLECT1)
6
EN_ APICK
Enables clock of MPUI clock:
R/W
0
0
MPUI clock stopped—bit must be set to logic 1 to
enable clock activity
1
MPUI clock active
5
RESERVED
Reserved. This bit should always be written as 0.
P R/W
0
Note:
When the timer/watchdog is configured as watchdog timer, the clock is never shutdown, regardless the value of the
IDLWDT_ARM bit or the EN_WDTCK bit.
