Camera Interface
7-12
7.2.1.10
Camera Interface Registers (FFFB:6800)
Because the TIPB register read accesses are resynchronized to the camera
interface clock, the MCLK_EN bit must first be set before any camera interface
register reads are performed. Table 7-3 lists the camera interface registers.
Table 7-4 through Table 7-10 describe the individual registers.
Table 7-3. Camera Interface Registers
Register
Description
R/W
Size
Offset
Address
CTRLCLOCK
Clock control
R/W
32 bits
0x00
IT_STATUS
Interrupt source status
R
32 bits
0x04
MODE
Camera interface mode configuration
R/W
32 bits
0x08
STATUS
Status
R
32 bits
0x0C
CAMDATA
Image data
R
32 bits
0x10
GPIO
Camera interface GPIO (general-purpose input/
output)
R/W
32 bits
0x14
PEAK_COUNTER
FIFO peak counter
R/W
32 bits
0x18
The MCLK_EN bit gates the 12-MHz master clock of the camera interface
to disable the clock when switching between two clock domains or to save
power consumption when the camera module is not used. To clear
PEAK_COUNTER, read all data in FIFO then write PEAK_COUNTER with 0.
Table 7-4. Clock Control Register (CTRLCLOCK)
Bit
Name
Value
Function
R/W
Reset
Value
31-8
RESERVED
This field is reserved (unknown value after
reset).
R/W
0xX
7
LCLK_EN
0
Disables
R/W
0x0
1
Enables incoming CAM.LCLK
6
DPLL_EN
0
Disables
R/W
0x0
1
Enables DPLL source (48 MHz)
5
MCLK_EN
0
Disables
R/W
0x0
1
Enables internal clock of interface
