ESI Operation
977
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Extended Scan Interface (ESI)
Table 37-5. TSM State Duration
ESICLK
For Previous State
For Current State
State Duration, T
0
0
T = (ESIR 1) x 1/f
ESIHFCLK
0
1
(ESIREPEATx) x 1/f
ACLK
< T
≤
(ESIR 1) x 1/f
ACLK
1
0
(ESIR 1) x 1/f
ESIHFCLK
≤
T < (ESIR 3) x 1/f
ESIHFCLK
1
1
T = (ESIR 1) x 1/f
ACLK
37.2.2.5 TSM State Clock Source Select
The TSM clock source is individually configurable for each state. The TSM can be clocked from ACLK or a
high frequency clock selected with the ESICLK bit. When ESICLK = 1, ACLK is used for the state, and
when ESICLK = 0, the high frequency clock is used. The high frequency clock can be sourced from
SMCLK or the TSM internal oscillator, selected by the ESIHFSEL bit. The high-frequency clock can be
divided by 1, 2, 4, or 8 with ESIDIV1x bits.
A set ESICLKON bit is used to turn on the selected high frequency clock source for the duration of the
state, when it is not used for the state. If the DCO is selected as the high frequency clock source, it is
automatically turned on, regardless of the low-power mode settings of the MSP430.
The TSM internal oscillator should be adjusted to the nominal frequency of 4.8 MHz. To realize this it can
be tuned in nominal 3% steps from around 1 MHz to around 8MHz with the ESICLKFQx. The frequency
and the steps differ from unit to unit. See the device-specific data sheet for parameters.
The TSM internal oscillator frequency can be measured with ACLK. When ESIHFSEL = 1 and
ESICLKGON = 1 ESICNT3 is reset, and beginning with the next rising edge of ACLK, ESICNT3 counts
the clock cycles of the internal oscillator. ESICNT3 counts the internal oscillator cycles for one ACLK
period. Reading ESICNT3 while it is counting will result in reading 01h.
The ACLK is automatically turned on for the following cases, regardless of the low-power mode settings of
the MSP430:
•
ACLK is automatically turned on all the time when the divided ACLK signal (ESIDIV2x, ESIDIV3Ax,
and ESIDIV3Bx dividers) is selected as trigger for starting a TSM sequence.
•
While a TSM sequence is in progress the ACLK is automatically turned on.
37.2.2.6 TSM Stop Condition
A TSM sequence always starts with ESITSM0, uses some ESITSMx states to do a measurement, and
ends at the subsequent ESITSMx state with a set ESISTOP bit (stop state). The duration of this last state
(stop state) is always one ESIHFCLK cycle regardless of the ESICLK or ESIREPEATx settings. The
ESIIFG1 interrupt flag is set at when the TSM encounters a state with a set ESISTOP bit.
37.2.2.7 TSM Test Cycles
For calibration purposes, to detect sensor drift, or to measure signals other than the sensor signals, a test
cycle may be inserted between TSM cycles by setting the ESITESTD bit. The time between the TSM
cycles is not altered by the test cycle insertion as shown in
. At the end of the test cycle the
ESITESTD bit is automatically cleared. The TESTDX signal is active during the test cycle to control input
and output channel selection. TESTDX is generated after the ESITESTD bit is set and the next TSM
sequence completes.