eUSCI_A Operation – UART Mode
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SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode
30.3.9.2 Oversampling Baud-Rate Generation
The oversampling mode is selected when UCOS16 = 1. This mode supports sampling a UART bitstream
with higher input clock frequencies. This results in majority votes that are always 1/16 of a bit clock period
apart. This mode also easily supports IrDA pulses with a 3/16 bit time when the IrDA encoder and decoder
are enabled.
This mode uses one prescaler and one modulator to generate the BITCLK16 clock that is 16 times faster
than the BITCLK. An additional divider by 16 and modulator stage generates BITCLK from BITCLK16.
This combination supports fractional divisions of both BITCLK16 and BITCLK for baud-rate generation. In
this mode, the maximum eUSCI_A baud rate is 1/16 the UART source clock frequency BRCLK.
Modulation for BITCLK16 is based on the UCBRFx setting (see
). A 1 in the table indicates that
the corresponding BITCLK16 period is one BRCLK period longer than the periods m = 0. The modulation
restarts with each new bit timing.
Modulation for BITCLK is based on the UCBRSx setting as previously described.
Table 30-3. BITCLK16 Modulation Pattern
UCBRFx
Number of BITCLK16 Clocks After Last Falling BITCLK Edge
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
00h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
01h
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
02h
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
03h
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
04h
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
05h
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
06h
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
07h
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
08h
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
09h
0
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0Ah
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0Bh
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0Ch
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0Dh
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0Eh
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0Fh
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1