RTC_C Registers
753
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Real-Time Clock C (RTC_C)
29.4.31 RTCPS0CTL Register
Real-Time Clock Prescale Timer 0 Control Register
(1)
The configuration of these bits is retained during LPMx.5 until LOCKLPM5 is cleared, but not the register bits themselves; therefore,
reconfiguration is required after wake-up from LPMx.5 before clearing LOCKLPM5.
Figure 29-34. RTCPS0CTL Register
15
14
13
12
11
10
9
8
Reserved
RT0PSDIV
(1)
Reserved
RT0PSHOLD
(1)
r0
r0
rw-(0)
rw-(0)
rw-(0)
r0
r0
rw-(1)
7
6
5
4
3
2
1
0
Reserved
RT0IP
(1)
RT0PSIE
RT0PSIFG
r0
r0
r0
rw-(0)
rw-(0)
rw-(0)
rw-0
rw-(0)
Table 29-35. RTCPS0CTL Register Description
Bit
Field
Type
Reset
Description
15-14
Reserved
R
0h
Reserved. Always reads as 0.
13-11
RT0PSDIV
RW
0h
Prescale timer 0 clock divide. These bits control the divide ratio of the RT0PS
counter. In real-time clock calendar mode, these bits are don't care for RT0PS
and RT1PS. RT0PS clock output is automatically set to /256. RT1PS clock
output is automatically set to /128.
000b = Divide by 2
001b = Divide by 4
010b = Divide by 8
011b = Divide by 16
100b = Divide by 32
101b = Divide by 64
110b = Divide by 128
111b = Divide by 256
10-9
Reserved
R
0h
Reserved. Always reads as 0.
8
RT0PSHOLD
RW
1h
Prescale timer 0 hold. In real-time clock calendar mode, this bit is don't care.
RT0PS is stopped by the RTCHOLD bit.
0b = RT0PS is operational
1b = RT0PS is held
7-5
Reserved
R
0h
Reserved. Always reads as 0.
4-2
RT0IP
RW
0h
Prescale timer 0 interrupt interval
000b = Divide by 2
001b = Divide by 4
010b = Divide by 8
011b = Divide by 16
100b = Divide by 32
101b = Divide by 64
110b = Divide by 128
111b = Divide by 256
1
RT0PSIE
RW
0h
Prescale timer 0 interrupt enable
0b = Interrupt not enabled
1b = Interrupt enabled
0
RT0PSIFG
RW
0h
Prescale timer 0 interrupt flag
0b = No time event occurred
1b = Time event occurred