V2
V3
V4
V5
V6
V1
V0
ESIQ6EN
Q7 . . . Q0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
ESI
Memory
State Table
ESICNT1
+1
-1
ESIEN
ESICNT1EN
ESICNT2
ESIIS2x
Q6
Q7
State
Latch
Output
Latch
Set_ESIIFG4
11
10
01
00
Set_ESIIFG5
Set_ESIIFG3
∆1
∆4
∆256
∆65536
ESISTOP(tsm)
0
1
ESIV2SEL
Q0
Q4
Q5
Q6
Q3
ESIQ7TRG
PPUS1
PPUS2
PPUS3
State
Current
Next
ESICNT0
ESICNT0EN
ESIIS0x
∆1
∆4
∆256
∆65536
11
10
01
00
Set_ESIIFG7
-1
+1
ESICNT2EN
0
1
0
ESICNT1RST
ESIEN
ESICNT0RST
ESIEN
ESICNT2RST
16
16
Comparator
00
01
10
11
ESITEST4
AFE1: ESIC1OUT
ESITEST4SEL
Q7
Set_ESIIFG6
TSM: TSM Clock
Comparator
ESITHR1
ESITHR2
16
V7
0
rst
As
Ds
ESI Operation
981
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Extended Scan Interface (ESI)
When ESICS = 1, the ESIEX(tsm) signal and the output bits PPUS1 and PPUS2 from the PPU can be
selected as inputs to Timer_A. This can be used to measure the duty cycle of PPUS1 or PPUS2.
37.2.5 ESI Processing State Machine
The PSM is a programmable state machine used to determine rotation and direction with its state table
stored within the ESI memory (ESI RAM). The processing state machine measures rotation and controls
interrupt generation based on the inputs from the timing state machine and the analog front-end. The PSM
block diagram is shown in
Figure 37-13. ESI Processing State Machine Block Diagram
37.2.5.1 PSM Operation
The PSM is triggered at any rising edge of ESISTOP(tsm) signal during a normal cycle. Note that a test
cycle insertion does not trigger the PSM. Triggering the PSM means, the PSM starts a sequence moving
the current-state byte (Q0...Q7) from the PSM state table located in ESI RAM to the PSM next state latch
(V2...V6 or V3...V6). All accesses to the PSM state table are done automatically with no CPU intervention.