RAMCTL Registers
336
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
RAM Controller (RAMCTL)
Table 10-2. CTL0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-2
RS1OFFx
R/W
0h
RAM controller RAM sector 1 off.
0h (R/W) = Contents of this RAM sector are retained in LPM3 and
LPM4.
1h (R/W) = Turns off this RAM sector in LPM3 and LPM4, re-
activates it on wake-up.
All data of this RAM sector is lost after wakeup from LPM3 and
LPM4. See the
device-specific data sheet to find the number of available sectors,
the address
range, and the size of each RAM sector.
2h (R/W) = Turns off this RAM sector entering LPM3 and LPM4, the
RAM sector
remains off after wake-up. All data of this RAM sector is lost. See the
devicespecific
data sheet to find the number of available sectors, the address
range,
and the size of each RAM sector.
1-0
RS0OFF
R/W
0h
RAM controller RAM sector 0 off
0h (R/W) = Contents of this RAM sector are retained in LPM3 and
LPM4.
1h (R/W) = Turns off this RAM sector in LPM3 and LPM4, re-
activates it on wake-up.
All data of this RAM sector is lost after wakeup from LPM3 and
LPM4. See the
device-specific data sheet to find the number of available sectors,
the address
range, and the size of each RAM sector.
2h (R/W) = Turns off this RAM sector entering LPM3 and LPM4, the
RAM sector
remains off after wake-up. All data of this RAM sector is lost. See the
devicespecific
data sheet to find the number of available sectors, the address
range,
and the size of each RAM sector.