S
S
11110 xx/W
A
SLA (2.)
A
P or S
Reception of own
address and data
bytes. All are
acknowledged.
UCRXIFG = 1
DATA
DATA
A
A
UCTR = 0 (Receiver)
UCSTTIFG = 1
Gen Call
A
UCTR = 0 (Receiver)
UCSTTIFG = 1
UCSTPIFG = 0
Reception of the
general call
address.
P or S
UCRXIFG = 1
DATA
DATA
A
A
S
11110 xx/W
A
SLA (2.)
A
UCTR = 0 (Receiver)
UCSTTIFG = 1
11110 xx/R
A
UCTR = 1 (Transmitter)
UCSTTIFG = 1
UCTXIFG = 1
DATA
A
P or S
Reception of own
address and
transmission of data
bytes
Slave Transmitter
Slave Receiver
UCSTPIFG = 0
UCGC = 1
UCSTPIFG = 0
UCSTPIFG = 0
eUSCI_B Operation – I
2
C Mode
831
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Enhanced Universal Serial Communication Interface (eUSCI) – I
2
C Mode
Figure 32-11. I
2
C Slave 10-Bit Addressing Mode
32.3.5.2 Master Mode
The eUSCI_B module is configured as an I
2
C master by selecting the I
2
C mode with UCMODEx = 11 and
UCSYNC = 1 and setting the UCMST bit. When the master is part of a multi-master system, UCMM must
be set and its own address must be programmed into the UCBxI2COA0 register. Support for multiple
slave addresses is explained in
. When UCA10 = 0, 7-bit addressing is selected. When
UCA10 = 1, 10-bit addressing is selected. The UCGCEN bit selects if the eUSCI_B module responds to a
general call.
NOTE:
Addresses and multi-master systems
In master mode with own-address detection enabled (UCOAEN = 1)—especially in multi-
master systems—it is not allowed to specify the same address in the own address and slave
address register (UCBxI2CSA = UCBxI2COAx). This would mean that the eUSCI_B
addresses itself.
The user software must ensure that this situation does not occur. There is no hardware
detection for this case, and the consequence is unpredictable behavior of the eUSCI_B.