RAMCTL Operation
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SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
RAM Controller (RAMCTL)
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A read access from CPU or DMA returns with 0x3FFF
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A instruction fetch access from CPU results in executing a jump $ instruction (0x3FFF)
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A read or write access from CPU or DMA causes the DACCESSIFG bit to be set
This conflict does not affect the access by the DTC. The DACCESS interrupt can be enabled or disabled
by the DACCESSIE bit. If DACCESSIE = 1 and DACCESSIFG = 1, then a user NMI is generated
(DACCESSIFG). See the device-specific data sheet for the user NMI information.