SAPH and SAPH_A Registers
565
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Sequencer for Acquisition, Programmable Pulse Generator, and Physical
Interface (SAPH, SAPH_A)
21.8.43 SAPHTBCTL/SAPH_ATBCTL Register (Offset = 7Ah) [reset = 0h]
SAPHTBCTL/SAPH_ATBCTL is shown in
and described in
.
Return to
Time Base Control Register
Figure 21-63. SAPHTBCTL/SAPH_ATBCTL Register
15
14
13
12
11
10
9
8
PSTAT
RESERVED
RESERVED
RESERVED
R-0h
R/W-0h
R-0h
R-0h
7
6
5
4
3
2
1
0
PSSV
RESERVED
TSTOP
TSTART
TCLR
R/W-0h
R/W-0h
W-0h
W-0h
W-0h
Table 21-48. SAPHTBCTL/SAPH_ATBCTL Register Field Descriptions
Bit
Field
Type
Reset
Description
15-14
PSTAT
R
0h
These bits reflect the current power state of the USS module. These
bits are also reflected in "energy trace" of the debug tools. As simple
unidirectional measurement sequence would show the sequence:
"0,1,2,1,3,1,0"
Reset type: PUC
0h (R/W) = ASQ inactive or waiting for trigger (ASQ timer not
running)
1h (R/W) = ASQ timer running (ASQ timer tuning)
2h (R/W) = PPG during ping process
3h (R/W) = ADC during acquisition process
13-10
RESERVED
R/W
0h
9
RESERVED
R
0h
Reserved
8
RESERVED
R
0h
Reserved
7-4
PSSV
R/W
0h
ASQ pre-scaler shift. The value written to the PSSV bits shifts the
start point of the ASQ's pre-scaler. Note that the value only affects
the first cycle of the pre-scaler.
0 = No shift
1 = The pre-scaler starts 1 clock later
2 = The pre-scaler starts 2 clocks later
...
15 = The pre-scaler starts 15 clocks later
Reset type: PUC
3
RESERVED
R/W
0h
2
TSTOP
W
0h
The ASQ time counter stop. Writing '1' to this bit stops the counter.
This bit is self cleared. TSTOP, TSTART, and TCLR bits are offerred
for only debugging purpose. It is not recommend to use this bit while
ASQ is active.
Note: This bit is write only. Reading always returns with zero.
1
TSTART
W
0h
The ASQ time counter start. Writing '1' to this bit starts the counter.
This bit is self cleared. TSTOP, TSTART, and TCLR bits are offerred
for only debugging purpose. It is not recommend to use this bit while
ASQ is active.
Note: This bit is write only. Reading always returns with zero.
0
TCLR
W
0h
The ASQ time counter clear. Writing '1' to this bit clears the the
counter value. The counter must be stopped prior to be cleared. This
bit is self cleared. TSTOP, TSTART, and TCLR bits are offerred for
only debugging purpose. It is not recommend to use this bit while
ASQ is active.
Note: This bit is write only. Reading always returns with zero.