COMP_E Registers
927
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Comparator E (COMP_E) Module
35.3.4 CECTL3 Register (offset = 06h) [reset = 0000h]
Comparator_E Control Register 3
Figure 35-11. CECTL3 Register
15
14
13
12
11
10
9
8
CEPD15
CEPD14
CEPD13
CEPD12
CEPD11
CEPD10
CEPD9
CEPD8
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
7
6
5
4
3
2
1
0
CEPD7
CEPD6
CEPD5
CEPD4
CEPD3
CEPD2
CEPD1
CEPD0
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
Table 35-5. CECTL3 Register Description
Bit
Field
Type
Reset
Description
15
CEPD15
RW
0h
Port disable. These bits individually disable the input buffer for the pins of the
port associated with Comparator_E. The bit CEPD15 disables the port of the
comparator channel 15.
0b = The input buffer is enabled.
1b = The input buffer is disabled.
14
CEPD14
RW
0h
Port disable. These bits individually disable the input buffer for the pins of the
port associated with Comparator_E. The bit CEPD14 disables the port of the
comparator channel 14.
0b = The input buffer is enabled.
1b = The input buffer is disabled.
13
CEPD13
RW
0h
Port disable. These bits individually disable the input buffer for the pins of the
port associated with Comparator_E. The bit CEPD13 disables the port of the
comparator channel 13.
0b = The input buffer is enabled.
1b = The input buffer is disabled.
12
CEPD12
RW
0h
Port disable. These bits individually disable the input buffer for the pins of the
port associated with Comparator_E. The bit CEPD12 disables the port of the
comparator channel 12.
0b = The input buffer is enabled.
1b = The input buffer is disabled.
11
CEPD11
RW
0h
Port disable. These bits individually disable the input buffer for the pins of the
port associated with Comparator_E. The bit CEPD11 disables the port of the
comparator channel 11.
0b = The input buffer is enabled.
1b = The input buffer is disabled.
10
CEPD10
RW
0h
Port disable. These bits individually disable the input buffer for the pins of the
port associated with Comparator_E. The bit CEPD10 disables the port of the
comparator channel 10.
0b = The input buffer is enabled.
1b = The input buffer is disabled.
9
CEPD9
RW
0h
Port disable. These bits individually disable the input buffer for the pins of the
port associated with Comparator_E. The bit CEPD9 disables the port of the
comparator channel 9.
0b = The input buffer is enabled.
1b = The input buffer is disabled.
8
CEPD8
RW
0h
Port disable. These bits individually disable the input buffer for the pins of the
port associated with Comparator_E. The bit CEPD8 disables the port of the
comparator channel 8.
0b = The input buffer is enabled.
1b = The input buffer is disabled.
7
CEPD7
RW
0h
Port disable. These bits individually disable the input buffer for the pins of the
port associated with Comparator_E. The bit CEPD7 disables the port of the
comparator channel 7.
0b = The input buffer is enabled.
1b = The input buffer is disabled.