Operating Modes
56
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
System Resets, Interrupts, and Operating Modes, System Control Module
(SYS)
1.4
Operating Modes
The MSP430 family is designed for ultralow-power applications and uses different operating modes shown
in
The operating modes take into account three different needs:
•
Ultra-low power
•
Speed and data throughput
•
Minimization of individual peripheral current consumption
The low-power modes LPM0 through LPM4 are configured with the CPUOFF, OSCOFF, SCG0, and
SCG1 bits in the SR. The advantage of including the CPUOFF, OSCOFF, SCG0, and SCG1 mode-control
bits in the SR is that the present operating mode is saved onto the stack during an interrupt service
routine. Program flow returns to the previous operating mode if the saved SR value is not altered during
the interrupt service routine. Program flow can be returned to a different operating mode by manipulating
the saved SR value on the stack inside of the interrupt service routine. When setting any of the mode-
control bits, the selected operating mode takes effect immediately. Peripherals operating with any disabled
clock are disabled until the clock becomes active. Peripherals may also be disabled with their individual
control register settings. All I/O port pins, RAM, and registers are unchanged. Wakeup from LPM0 through
LPM4 is possible through all enabled interrupts.
When LPMx.5 (LPM3.5 or LPM4.5) is entered, the voltage regulator of the Power Management Module
(PMM) is disabled. All RAM and register contents are lost. Although the I/O register contents are lost, the
I/O pin states are locked upon LPMx.5 entry. See the
chapter for further details. Wakeup from
LPM4.5 is possible through a power sequence, a RST event, or from specific I/O. Wakeup from LPM3.5 is
possible through a power sequence, a RST event, RTC event, or from specific I/O.
NOTE:
The TEST/SBWTCK pin is used to enable the connection of external development tools with
the device through Spy-Bi-Wire or JTAG debug protocols. The connection is usually enabled
when the TEST/SBWTCK is high. When the connection is enabled the device enters a
debug mode. In the debug mode the entry and wake-up times to and from low power modes
may be different compared to normal operation. Pay careful attention to the real-time
behavior when using low power modes with the device connected to a development tool!
See the
chapter for further details.