Instruction Set Description
241
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
CPUX
4.6.3.27 RRCM
RRCM.A
Rotate right through carry the 20-bit CPU register content
RRCM.[W]
Rotate right through carry the 16-bit CPU register content
Syntax
RRCM.A #n,Rdst
1
≤
n
≤
4
RRCM.W #n,Rdst
or
RRCM #n,Rdst
1
≤
n
≤
4
Operation
C
→
MSB
→
MSB–1 ... LSB+1
→
LSB
→
C
Description
The destination operand is shifted right by 1, 2, 3, or 4 bit positions as shown in
. The carry bit C is shifted into the MSB, the LSB is shifted into the carry bit.
The word instruction RRCM.W clears the bits Rdst.19:16.
Note : This instruction does not use the extension word.
Status Bits
N:
Set if result is negative
.A: Rdst.19 = 1, reset if Rdst.19 = 0
.W: Rdst.15 = 1, reset if Rdst.15 = 0
Z:
Set if result is zero, reset otherwise
C:
Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3), or LSB+3 (n = 4)
V:
Reset
Mode Bits
OSCOFF, CPUOFF, and GIE are not affected.