SDHS Registers
607
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Sigma-Delta High Speed (SDHS)
22.5.10 SDHSCTL1 Register (Offset = 12h) [reset = 0h]
SDHSCTL1 is shown in
and described in
Return to
SDHS Control Register 1
When SDHSCTL3.TRGEN = 1 or SDHSCTL5.SDHS_LOCK = 1, this register is locked. In that case, an
attempt to update this registers will be ignored.
Figure 22-36. SDHSCTL1 Register
15
14
13
12
11
10
9
8
Reserved
R-0h
7
6
5
4
3
2
1
0
Reserved
OSR
R-0h
R/W-0h
Table 22-21. SDHSCTL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-4
Reserved
R
0h
Reserved. Always reads as 0.
3-0
OSR
R/W
0h
Over Sampling Rate. Output Data Rate = Input Clock Frequency /
OSR.
Note: values not shown below are reserved.
Reset type: PUC
0h (R/W) = 10
1h (R/W) = 20
2h (R/W) = 40
3h (R/W) = 80
4h (R/W) = 160