ENNMI
DMA Channel n
DMASRSBYTE
DMAnSZ
DMAnDA
DMAnSA
DMADSTBYTE
DMASRCINCR
DMADSTINCR
2
2
3
DMADT
DMAEN
DMA Channel1
DMASRSBYTE
DMA1SZ
DMA1DA
DMA1SA
DMADSTBYTE
DMASRCINCR
DMADSTINCR
2
2
3
DMADT
DMAEN
DMA Channel 0
DMASRSBYTE
DMA0SZ
DMA0DA
DMA0SA
DMADSTBYTE
DMASRCINCR
DMADSTINCR
2
2
3
DMADT
DMAEN
Address
Space
NMI Interrupt Request
JTAG Active
Halt
Halt CPU
ROUNDROBIN
DMARMWDIS
DMAnTSEL
DMA0TRIG31
DMA0TRIG0
DMA0TSEL
5
DMA0TRIG1
00000
00001
11111
DMA1TRIG31
DMA1TRIG0
DMA1TSEL
5
DMA1TRIG1
00000
00001
11111
DMAnTRIG31
DMAnTRIG0
5
DMAnTRIG1
00000
00001
11111
D
MA
Pr
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a
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d
C
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Direct Memory Access (DMA) Introduction
340
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
DMA Controller
Figure 11-1. DMA Controller Block Diagram