AES Accelerator Operation
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SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
AES256 Accelerator
14.2.8 AES Key Buffer
The AES128, AES192, or AES256 algorithm operates not only on the state but also on the key. To avoid
the need of reloading the key for each encryption or decryption, a key buffer is included in the AES
accelerator.
14.2.9 Using the AES Accelerator With Low-Power Modes
The AES accelerator module provides automatic clock activation for MCLK for use with low-power modes.
When the AES accelerator is busy, it automatically activates MCLK, regardless of the control-bit settings
for the clock source. The clock remains active until the AES accelerator completes its operation.
The interrupt flag AESRDYIFG is reset after a PUC or with AESSWRST = 1. AESRDYIE is reset after a
PUC but is not reset by AESSWRST = 1.
14.2.10 AES Accelerator Interrupts
The AESRDYIFG interrupt flag is set when the AES module completes the selected operation on the
provided data. An interrupt request is generated if AESRDYIE and GIE are also set. AESRDYIFG is
automatically reset if the AES interrupt is serviced, if AESADOUT is read, or if AESADIN or AESAKEY are
written. AESRDYIFG is reset after a PUC or with AESSWRST = 1. AESRDYIE is reset after a PUC but is
not reset by AESSWRST = 1.
14.2.11 DMA Operation and Implementing Block Cipher Modes
DMA operation, meaning the implementation of the cipher modes Electronic code book (ECB), Cipher
block chaining (CBC), Output feedback (OFB), and Cipher feedback (CFB) using the DMA, supports easy
and fast encryption and decryption of more than 128 bits.
When DMA cipher mode support is enabled by setting the AESCMEN bit, the AES256 module triggers
'AES trigger 0', 'AES trigger 1', and 'AES trigger 2' (also called 'AES trigger 0-2') in a certain order to
execute different block cipher modes together with the DMA module.
For example, when using ECB encryption with AESCMEN = 1, 'AES trigger 0' is triggered eight times for
DMA word access to read out AESADOUT, and then 'AES trigger 1' is triggered eight times to fill the next
data into AESADIN. Because the AES modules generates a trigger for each word or byte the single
transfer mode of the DMA must be used.