SFR Registers
74
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
System Resets, Interrupts, and Operating Modes, System Control Module
(SYS)
1.15.2 SFRIFG1 Register
Interrupt Flag Register
(1)
See the
chapter for details.
(2)
See the
chapter for details.
Figure 1-8. SFRIFG1 Register
15
14
13
12
11
10
9
8
Reserved
r0
r0
r0
r0
r0
r0
r0
r0
7
6
5
4
3
2
1
0
JMBOUTIFG
JMBINIFG
Reserved
NMIIFG
VMAIFG
Reserved
OFIFG
(1)
WDTIFG
(2)
rw-(1)
rw-(0)
r0
rw-0
rw-0
r0
rw-(1)
rw-0
Table 1-14. SFRIFG1 Register Description
Bit
Field
Type
Reset
Description
15-8
Reserved
R
0h
Reserved. Always reads as 0.
7
JMBOUTIFG
RW
1h
JTAG mailbox output interrupt flag
0b = No interrupt pending. When in 16-bit mode (JMBMODE = 0), this bit is
cleared automatically when JMBO0 has been written with a new message to the
JTAG module by the CPU. When in 32-bit mode (JMBMODE = 1), this bit is
cleared automatically when both JMBO0 and JMBO1 have been written with new
messages to the JTAG module by the CPU. This bit is also cleared when the
associated vector in SYSUNIV has been read.
1b = Interrupt pending, JMBO registers are ready for new messages. In 16-bit
mode (JMBMODE = 0), JMBO0 has been received by the JTAG module and is
ready for a new message from the CPU. In 32-bit mode (JMBMODE = 1) ,
JMBO0 and JMBO1 have been received by the JTAG module and are ready for
new messages from the CPU.
6
JMBINIFG
RW
0h
JTAG mailbox input interrupt flag
0b = No interrupt pending. When in 16-bit mode (JMBMODE = 0), this bit is
cleared automatically when JMBI0 is read by the CPU. When in 32-bit mode
(JMBMODE = 1), this bit is cleared automatically when both JMBI0 and JMBI1
have been read by the CPU. This bit is also cleared when the associated vector
in SYSUNIV has been read
1b = Interrupt pending, a message is waiting in the JMBIN registers. In 16-bit
mode (JMBMODE = 0) when JMBI0 has been written by the JTAG module. In
32-bit mode (JMBMODE = 1) when JMBI0 and JMBI1 have been written by the
JTAG module.
5
Reserved
R
0h
Reserved. Always reads as 0.
4
NMIIFG
RW
0h
NMI pin interrupt flag
0b = No interrupt pending
1b = Interrupt pending
3
VMAIFG
RW
0h
Vacant memory access interrupt flag
0b = No interrupt pending
1b = Interrupt pending
2
Reserved
R
0h
Reserved. Always reads as 0.
1
OFIFG
RW
1h
Oscillator fault interrupt flag
0b = No interrupt pending
1b = Interrupt pending
0
WDTIFG
RW
0h
Watchdog timer interrupt flag. In watchdog mode, WDTIFG clears itself upon a
watchdog timeout event. The SYSRSTIV can be read to determine if the reset
was caused by a watchdog timeout event. In interval mode, WDTIFG is reset
automatically by servicing the interrupt, or can be reset by software. Because
other bits in SFRIFG1 may be used for other modules, it is recommended to set
or clear WDTIFG by using BIS.B or BIC.B instructions, rather than MOV.B or
CLR.B instructions.
0b = No interrupt pending
1b = Interrupt pending