eUSCI_B I2C Registers
854
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Enhanced Universal Serial Communication Interface (eUSCI) – I
2
C Mode
32.4.11 UCBxI2COA3 Register
eUSCI_Bx I2C Own Address 3 Register
Figure 32-27. UCBxI2COA3 Register
15
14
13
12
11
10
9
8
Reserved
UCOAEN
I2COA3
rw-0
r0
r0
r0
r0
rw-0
rw-0
rw-0
7
6
5
4
3
2
1
0
I2COA3
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
Can be modified only when UCSWRST = 1.
Table 32-14. UCBxI2COA3 Register Description
Bit
Field
Type
Reset
Description
15-11
Reserved
R
0h
Reserved
10
UCOAEN
RW
0h
Own Address enable register. With this register it can be selected if the I2C
slave-address related to this register UCBxI2COA3 is evaluated or not.
Modify only when UCSWRST = 1.
0b = The slave address defined in I2COA3 is disabled
1b = The slave address defined in I2COA3 is enabled
9-0
I2COA3
RW
0h
I2C own address. The I2COA3 bits contain the local address of the eUSCIx_B
I2C controller. The address is right justified. In 7-bit addressing mode, bit 6 is the
MSB and bits 9-7 are ignored. In 10-bit addressing mode, bit 9 is the MSB.
Modify only when UCSWRST = 1.
32.4.12 UCBxADDRX Register
eUSCI_Bx I2C Received Address Register
Figure 32-28. UCBxADDRX Register
15
14
13
12
11
10
9
8
Reserved
ADDRXx
r-0
r0
r0
r0
r0
r0
r-0
r-0
7
6
5
4
3
2
1
0
ADDRXx
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
Table 32-15. UCBxADDRX Register Description
Bit
Field
Type
Reset
Description
15-10
Reserved
R
0h
Reserved
9-0
ADDRXx
R
0h
Received Address Register. This register contains the last received slave
address on the bus. Using this register and the address mask register it is
possible to react on more than one slave address using one eUSCI_B module.