eUSCI_B Operation – I
2
C Mode
840
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Enhanced Universal Serial Communication Interface (eUSCI) – I
2
C Mode
32.3.9.1 Multiple Slave Address Registers
The registers UCBxI2COA0, UCBxI2COA1, UCBxI2COA2, and UCBxI2COA3 contain four slave addresses. Up to four address registers are
compared against a received 7- or 10-bit address. Each slave address must be activated by setting the UCAOEN bit in the corresponding
UCBxI2COAx register. Register UCBxI2COA3 has the highest priority if the address received on the bus matches more than one of the slave
address registers. The priority decreases with the index number of the address register, so that UCBxI2COA0 in combination with the address
mask has the lowest priority.
When one of the slave registers matches the 7- or 10-bit address seen on the bus, the address is acknowledged. In the following the
corresponding receive- or transmit-interrupt flag (UCTXIFGx or UCRXIFGx) to the received address is updated. The state change interrupt flags
are independent of the address comparison result. They are updated according to the bus condition.
32.3.9.2 Address Mask Register
The address mask register can be used when the eUSCI_B is configured in slave or in multiple-master mode. To activate this feature, at least one
bit of the address mask in register UCBxADDMASK must be cleared.
If the received address matches the own address in UCBxI2COA0 on all bit positions that are not masked by UCBxADDMASK, the eUSCI_B
module considers the received address as its own address. If UCSWACK = 0, the module sends an acknowledge automatically. If UCSWACK = 1,
the user software must evaluate the received address in register UCBxADDRX after the UCSTTIFG is set. To acknowledge the received address,
the software must set UCTXACK to 1.
The eUSCI_B module also automatically acknowledges a slave address that is seen on the bus if the address matches any of the enabled slave
addresses defined in UCBxI2COA1 to UCBxI2COA3.
NOTE:
UCSWACK and slave-transmitter
If the user selects manual acknowledge of slave addresses, TXIFG is set if the slave is addressed as a transmitter. If the software
decides not to acknowledge the address, TXIFG0 must be reset.
32.3.10 Using the eUSCI_B Module in I
2
C Mode With Low-Power Modes
The eUSCI_B module provides automatic clock activation for use with low-power modes. When the eUSCI_B clock source is inactive because the
device is in a low-power mode, the eUSCI_B module automatically activates it when needed, regardless of the control-bit settings for the clock
source. The clock remains active until the eUSCI_B module returns to its idle condition. After the eUSCI_B module returns to the idle condition,
control of the clock source reverts to the settings of its control bits.
In I
2
C slave mode, no internal clock source is required because the clock is provided by the external master. It is possible to operate the eUSCI_B
in I
2
C slave mode while the device is in LPM4 and all internal clock sources are disabled. The receive or transmit interrupts can wake up the CPU
from any low-power mode.
32.3.11 eUSCI_B Interrupts in I
2
C Mode
The eUSCI_B has only one interrupt vector that is shared for transmission, reception, and the state change.