Connection of Unused Pins
62
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
System Resets, Interrupts, and Operating Modes, System Control Module
(SYS)
•
Avoid frequent subroutine and function calls due to overhead.
•
For longer software routines, single-cycle CPU registers should be used.
If the application has low duty cycle and slow response time events, maximizing time in LPMx.5 can
further reduce power consumption significantly.
1.6
Connection of Unused Pins
The correct termination of all unused pins is listed in
.
(1)
Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin
connection guidelines.
(2)
The pulldown capacitor should not exceed 2.2 nF when using devices in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools
like FET interfaces or GANG programmers. If JTAG or Spy-Bi-Wire access is not needed, up to a 10-nF pulldown capacitor may
be used.
Table 1-4. Connection of Unused Pins
(1)
Pin
Potential
Comment
AVCC
DV
CC
AVSS
DV
SS
Px.0 to Px.7
Open
Switched to port function, output direction (PxDIR.n = 1)
RST/NMI
DV
CC
or V
CC
47-k
Ω
pullup or internal pullup selected with 2.2-nF (10-nF
(2)
) pulldown
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
Open
The JTAG pins are shared with general-purpose I/O function (PJ.x). If not being used, these
should be switched to port function, output direction. When used as JTAG pins, these pins
should remain open.
TEST
Open
This pin always has an internal pulldown enabled.
1.7
Reset Pin (RST/NMI) Configuration
The reset pin can be configured as a reset function (default) or as an NMI function through the Special
Function Register (SFR), SFRRPCR. Setting SYSNMI causes the RST/NMI pin to be configured as an
external NMI source. The external NMI is edge sensitive and its edge is selectable by SYSNMIIES.
Setting the NMIIE enables the interrupt of the external NMI. Upon an external NMI event, the NMIIFG is
set.
The RST/NMI pin can have either a pullup or pulldown present or not. SYSRSTUP selects either pullup or
pulldown, and SYSRSTRE causes the pullup or pulldown to be enabled or not. If the RST/NMI pin is
unused, it is required to have either the internal pullup selected and enabled or an external resistor
connected to the RST/NMI pin as shown in
There is a digital filter that suppresses short pulses on the reset pin to avoid unintended resets of the
device. The minimum reset pulse duration is specified in the device data sheet. The filter is active only if
the pin is configured in its reset function. The filter is disabled if the pin is used as an external NMI source.
1.8
Configuring JTAG Pins
The JTAG pins are shared with general-purpose I/O pins. After a BOR, the SYSJTAGPIN bit in the
SYSCTL register is cleared. With SYSJTAGPIN cleared, the pins with JTAG functionality are configured
as general-purpose I/O. In this case only a special sequences on the TEST and RST/NMI pins enables
the JTAG functionality. As long as the TEST pin is pulled to DVCC, the pins remain in their JTAG
functionality. If the TEST pin is released to DVSS, the shared JTAG pins revert to general-purpose I/Os.
If SYSJTAGPIN = 1, the JTAG pins are permanently configured to 4-wire JTAG mode and remain in this
mode until another BOR occurs. Use this feature early in your software if the MSP430 is part of a JTAG
chain. Note, that this also disables the Spy-Bi-Wire mode.
The SYSJTAGPIN is a write only once function. Clearing it by software is not possible.