FRCTL_A Registers
306
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
FRAM Controller A (FRCTL_A)
Table 8-4. FRCTL0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3
AUTO
R/W
0h
Enable automatic Wait State Mode.
Reset type: BOR
0h (R/W) = AUTO_0 : User Wait State Mode. The NWAITS[3:0] is
used for the FRAM wait state.
1h (R/W) = AUTO_1 : Auto mode. The NWAITS[3:0] is ignored. Wait
states are generated automatically by the internal FRAM controller
state machine.
2-1
Reserved
R
0h
Reserved. Always read 0.
Reset type: PUC
0
WPROT
R/W
0h
Write Protection Enable.
This bit is set after BOR. This bit must be cleared before accessing
FRAM for write. This bit does not block read operation. Note that the
WPROT bit protects the entire FRAM memory from unintended write,
so it should be used as temporary protection. If it is desired to
protect a portion of the FRAM memory permanently, it should be
done via MPU segments. See the MPU module for details.
Reset type: BOR
0h (R/W) = WPROT_0 : Disable Write Protection. Write to FRAM
memory is allowed.
1h (R/W) = WPROT_1 : Enable Write Protection. Write to FRAM
memory is not allowed. If a write access is attempted, the WPIFG
(Write Protection Flag) bit will be set.