ADC12_B Registers
894
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
ADC12_B
Table 34-4. ADC12CTL0 Register Description (continued)
Bit
Field
Type
Reset
Description
7
ADC12MSC
RW
0
ADC12_B multiple sample and conversion. Valid only for sequence or repeated
modes. Can be modified only when ADC12ENC = 0.
0b = The sampling timer requires a rising edge of the SHI signal to trigger each
sample-and-convert.
1b = The incidence of the first rising edge of the SHI signal triggers the sampling
timer, but further sample-and-conversions are performed automatically as soon
as the prior conversion is completed.
6-5
Reserved
R
0
Reserved. Always reads as 0.
4
ADC12ON
RW
0
ADC12_B on. Can be modified only when ADC12ENC = 0.
0b = ADC12_B off
1b = ADC12_B on
3-2
Reserved
R
0
Reserved. Always reads as 0.
1
ADC12ENC
RW
0
ADC12_B enable conversion.
0b = ADC12_B disabled
1b = ADC12_B enabled
0
ADC12SC
RW
0
ADC12_B start conversion. Software-controlled sample-and-conversion start.
ADC12SC and ADC12ENC may be set together with one instruction. ADC12SC
is reset automatically.
0b = No sample-and-conversion-start
1b = Start sample-and-conversion