MAB
MDB
Control Registers
MPU
FRAM
Controller
Violation
Cache
FRAM
Memory
Array
FRAM Introduction
290
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
FRAM Controller (FRCTL)
7.1
FRAM Introduction
FRAM is a nonvolatile memory that reads and writes like standard SRAM. The MSP430 FRAM features
include:
•
Byte or word write access
•
Automatic and programmable wait state control with independent wait state settings for access and
cycle times
•
Error correction code with bit error correction, extended bit error detection and flag indicators
•
Cache for fast read
•
Power control for disabling FRAM if it is not used
For important software design information regarding FRAM, including but not limited to partitioning the
memory layout according to application-specific code, constant, and data space requirements, the use of
FRAM to optimize application energy consumption, and the use of the memory protection unit (MPU) to
maximize application robustness by protecting the program code against unintended write accesses, see
MSP430™ FRAM Technology – How To and Best Practices
shows the block diagram of the FRAM Controller.
Figure 7-1. FRAM Controller Block Diagram
7.2
FRAM Organization
The FRAM can be arranged into segments by the Memory Protection Unit (MPU). See
Memory
Protection Unit
, for details. The address space is linear with the exception of the User Information Memory
and the Device Descriptor Information (TLV).
7.3
FRCTL Module Operation
The FRAM can be read in a similar fashion to SRAM and needs no special requirements. Similarly, any
writes to unprotected segments can be written in the same fashion as SRAM. All writes to user protected
segments are handled as described in
Memory Protection Unit
.
An FRAM read always requires a write back to the same memory location with the same information read.
This write back is part of the FRAM module itself and requires no user interaction. These write backs are
different from the normal write access from application code.
The FRAM module has built-in error correction code (ECC) logic that can correct bit errors and detect
multiple bit errors. Two flags are available that indicate the presence of an error. The CBDIFG is set when
a correctable bit error has been detected. If CBDIE is also set, a System NMI event (SYSNMI) occurs.
The UBDIFG is set when a multiple bit error that is not correctable has been detected. If UBDIE is also
set, a System NMI event (SYSNMI) occurs. Upon correctable or uncorrectable bit errors, the program
vectors to the SYSSNIV if the NMI is enabled. If desired, a System Reset event (SYSRST) can be
generated by setting the UBDRSTEN bit. If an uncorrectable error is detected, a PUC is initiated and the
program vectors to the SYSRSTIV.