ESI Registers
1004
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Extended Scan Interface (ESI)
Table 37-22. ESIAFE Register Description (continued)
Bit
Field
Type
Reset
Description
(1)
The control bit ESIVSS was renamed to ESISHTSM to avoid confusion with supply pin naming.
(2)
The control bit ESIVCC2 was renamed to ESIVMIDEN to avoid confusion with supply pin naming.
3
ESISHTSM
(1)
RW
0h
Sample-and-hold ESIDVSS select.
0b = The ground connection of the sample capacitor is connected to ESIDVSS,
regardless of the TSM control.
1b = The ground connection of the sample capacitor is controlled by the TSM
2
ESIVMIDEN
(2)
RW
0h
Mid-voltage generator
0b = AVCC/2 generator is off
1b = AVCC/2 generator is on if ESISH = 0
1
ESISH
RW
0h
Sample-and-hold enable
0b = Sample-and-hold is disabled
1b = Sample-and-hold is enabled
0
ESITEN
RW
0h
Excitation enable
0b = Excitation circuitry is disabled
1b = Excitation circuitry is enabled