ADC12_B Registers
897
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
ADC12_B
34.3.3 ADC12CTL2 Register (offset = 04h) [reset = 0020h]
ADC12_B Control 2 Register
Figure 34-16. ADC12CTL2 Register
15
14
13
12
11
10
9
8
Reserved
r0
r0
r0
r0
r0
r0
r0
r0
7
6
5
4
3
2
1
0
Reserved
ADC12RES
ADC12DF
Reserved
ADC12PWRMD
r0
r0
rw-(1)
rw-(0)
rw-(0)
r0
r0
rw-(0)
Table 34-6. ADC12CTL2 Register Description
Bit
Field
Type
Reset
Description
15-6
Reserved
R
0h
Reserved. Always reads as 0.
5-4
ADC12RES
RW
2h
ADC12_B resolution. This bit defines the conversion result resolution. This bit
should only be modified when ADC12ENC=0.
00b = 8 bit (10 clock cycle conversion time)
01b = 10 bit (12 clock cycle conversion time)
10b = 12 bit (14 clock cycle conversion time)
11b = Reserved
3
ADC12DF
RW
0h
ADC12_B data read-back format. Data is always stored in the binary unsigned
format.
0b = Binary unsigned. Theoretically for ADC12DIF = 0 and 12-bit mode the
analog input voltage – VREF results in 0000h, the analog input v VREF
results in 0FFFh.
1b = Signed binary (2s complement), left aligned. Theoretically, for
ADC12DIF = 0 and 12-bit mode, the analog input voltage – VREF results in
8000h, the analog input v VREF results in 7FF0h.
2-1
Reserved
R
0h
Reserved. Always reads as 0.
0
ADC12PWRMD
RW
0h
Enables ADC low-power mode for ADC12CLK with 1/4 the specified maximum
for ADC12PWRMD = 0. This bit should only be modified when ADC12ENC = 0.
0b = Regular power mode where sample rate is not restricted
1b = Low power mode enable, ADC12CLK can not be greater than 1/4 the
device-specific data sheet specified maximum for ADC12PWRMD = 0