ESI Registers
1002
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Extended Scan Interface (ESI)
Table 37-21. ESIINT2 Register Description (continued)
Bit
Field
Type
Reset
Description
2
ESIIFG2
RW
0h
ESI interrupt flag 2. This bit is set at the start of a TSM sequence generated by
the divided ACLK. A TSM sequence started with ESISTART bit does not set
ESIIFG2. ESIIFG2 must be reset with software.
0b = No interrupt pending
1b = Interrupt pending
1
ESIIFG1
RW
0h
ESI interrupt flag 1. This bit is set by the rising edge of the ESISTOP(tsm) signal.
ESIIFG1 must be reset with software.
0b = No interrupt pending
1b = Interrupt pending
0
ESIIFG0
RW
0h
ESI interrupt flag 0. This bit is set by the AFE1's ESIOUTx conditions selected by
the ESIIFGSET1x bits. ESIIFG0 must be reset with software.
0b = No interrupt pending
1b = Interrupt pending