ESI Registers
1005
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Extended Scan Interface (ESI)
37.3.14 ESIPPU Register
Extended Scan Interface Pre-Processing Unit Control Register
Figure 37-35. ESIPPU Register
15
14
13
12
11
10
9
8
Reserved
ESITCHOUT1
ESITCHOUT0
r0
r0
r0
r0
r0
r0
r-(0)
r-(0)
7
6
5
4
3
2
1
0
ESIOUT7
ESIOUT6
ESIOUT5
ESIOUT4
ESIOUT3
ESIOUT2
ESIOUT1
ESIOUT0
r-(0)
r-(0)
r-(0)
r-(0)
r-(0)
r-(0)
r-(0)
r-(0)
Table 37-23. ESIPPU Register Description
Bit
Field
Type
Reset
Description
15-10
Reserved
R
0h
Reserved. These bits are always read as zero and, when written, do not affect
the bit setting.
9
ESITCHOUT1
R
0h
Latched AFE1 comparator output for test channel 1
8
ESITCHOUT0
R
0h
Latched AFE1 comparator output for test channel 0
7
ESIOUT7
R
0h
Latched AFE2 comparator output when ESICH3 input is selected
6
ESIOUT6
R
0h
Latched AFE2 comparator output when ESICH2 input is selected
5
ESIOUT5
R
0h
Latched AFE2 comparator output when ESICH1 input is selected
4
ESIOUT4
R
0h
Latched AFE2 comparator output when ESICH0 input is selected
3
ESIOUT3
R
0h
Latched AFE1 comparator output when ESICH3 input is selected
2
ESIOUT2
R
0h
Latched AFE1 comparator output when ESICH2 input is selected
1
ESIOUT1
R
0h
Latched AFE1 comparator output when ESICH1 input is selected
0
ESIOUT0
R
0h
Latched AFE1 comparator output when ESICH0 input is selected