15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
1
00
ZC
#
A/L
Rsvd
(n−1)/Rn
Op-code
Rsrc
Ad
B/W
As
Rdst
XORX.A
R9,R8
0
0
0
1
1
0
0
0
0
0
0
14(XOR)
9
0
1
0
8(R8)
XORX instruction
Source R9
0: Use Carry
1: Repetition count
in bits 3:0
01: Address word
Destination
register mode
Source
register mode
Destination R8
MSP430 and MSP430X Instructions
147
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
CPUX
Table 4-12. Description of Extension Word Bits for Non-Register Modes
Bit
Description
15:11
Extension word op-code. Op-codes 1800h to 1FFFh are extension words.
Source Bits
19:16
The 4 MSBs of the 20-bit source. Depending on the source addressing mode, these 4 MSBs may belong to an
immediate operand, an index, or to an absolute address.
A/L
Data length extension. Together with the B/W bits of the following MSP430 instruction, the AL bit defines the used
data length of the instruction.
A/L
B/W Comment
0
0
Reserved
0
1
20-bit address word
1
0
16-bit word
1
1
8-bit byte
5:4
Reserved
Destination
Bits 19:16
The 4 MSBs of the 20-bit destination. Depending on the destination addressing mode, these 4 MSBs may belong to
an index or to an absolute address.
NOTE:
B/W and A/L bit settings for SWPBX and SXTX
A/L
B/W
0
0
SWPBX.A, SXTX.A
0
1
N/A
1
0
SWPB.W, SXTX.W
1
1
N/A
Figure 4-27. Example for Extended Register or Register Instruction