COMP_E Registers
929
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Comparator E (COMP_E) Module
35.3.5 CEINT Register (offset = 0Ch) [reset = 0000h]
Comparator_E Interrupt Control Register
Figure 35-12. CEINT Register
15
14
13
12
11
10
9
8
Reserved
CERDYIE
Reserved
CEIIE
CEIE
r-0
r-0
r-0
rw-0
r-0
r-0
rw-0
rw-0
7
6
5
4
3
2
1
0
Reserved
CERDYIFG
Reserved
CEIIFG
CEIFG
r-0
r-0
r-0
rw-0
r-0
r-0
rw-0
rw-0
Table 35-6. CEINT Register Description
Bit
Field
Type
Reset
Description
15-13
Reserved
R
0h
Reserved. Reads as 0.
12
CERDYIE
RW
0h
Comparator_E ready interrupt enable.
0b = Interrupt is disabled
1b = Interrupt is enabled
11-10
Reserved
R
0h
Reserved. Reads as 0.
9
CEIIE
RW
0h
Comparator_E output interrupt enable inverted polarity
0b = Interrupt is disabled
1b = Interrupt is enabled
8
CEIE
RW
0h
Comparator_E output interrupt enable
0b = Interrupt is disabled
1b = Interrupt is enabled
7-5
Reserved
R
0h
Reserved. Reads as 0.
4
CERDYIFG
RW
0h
Comparator_E ready interrupt flag. This bit is set if the Comparator_E reference
sources are settled and the Comparator_E module is operational. This bit has to
be cleared by software.
0b = No interrupt pending.
1b = Output interrupt pending.
3-2
Reserved
R
0h
Reserved. Reads as 0.
1
CEIIFG
RW
0h
Comparator_E output inverted interrupt flag. The bit CEIES defines the transition
of the output setting this bit.
0b = No interrupt pending.
1b = Output interrupt pending.
0
CEIFG
RW
0h
Comparator_E output interrupt flag. The bit CEIES defines the transition of the
output setting this bit.
0b = No interrupt pending.
1b = Output interrupt pending.