FRAM Controller A (FRCTL_A) Operation
301
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
FRAM Controller A (FRCTL_A)
8.2.3.4
Timing Violation Detection
In user wait state mode (AUTO = 0), if NWAITS[3:0] bit has been configured with an incorrect wait state, a
timing violation can occur when accessing FRAM. Upon detecting a timing violation, the FRAM controller
responses to the timing violation event with three actions:
•
Sets the access timer error flag (ACCTEIFG)
•
Ignores the NWAITS[3:0] bits and internally applies the maximum wait state (15) (the NWAITS[3:0] bits
are not changed)
•
Flushes the cache
•
Disables write access to FRAM regardless of the WPROT bit (the WPROT bit is not changed)
The FRAM controller A (FRCTL_A) keeps the maximum wait state and blocks write access if the
ACCTEIFG bit is set in order to avoid further timing violations. It is recommended to configure the
NWAITS[3:0] bits based on the table shown in
and complete any necessary actions prior to
clearing the ACCTEIFG bit. When the ACCTEIFG bit is cleared, the FRAM controller A (FRCTL_A) takes
the value written to NWAITS[3:0] bits as wait state and enables write access to the FRAM if the WPROT
bit is cleared. The timing violation (ACCTEIFG) generates a system NMI (SYSNMI) if the access time
error interrupt enable (ACCTEIE) bit is set.
8.2.3.5
Automatic Wait State Mode
Automatic wait state mode is enabled when the AUTO bit is set. In this mode, the FRAM controller A
(FRCTL_A) takes a control of choosing a wait state. So, it is not required for user to configure
NWAITS[3:0] bits. The value written to NWAITS[3:0] has no influence in this mode. In order to determine
the wait state automatically, the FRAM controller A (FRCTL_A) adds a delay so that no maximum FRAM
access speed is reached and no timing violation is guaranteed. See
for wait state numbers in
automatic mode with different system frequencies.
Table 8-1. FRAM memory Access Speed
System Bus
Frequency
Required Wait States
FRAM Access Speed
(Without Cache Hit)
User Mode
Automatic Mode
User Mode
Automatic Mode
4 MHz
0
3
4 MHz
1 MHz
8 MHz
0
3
8 MHz
2 MHz
10 MHz
1
3
5 MHz
2.5 MHz
12 MHz
1
3
6 MHz
3 MHz
14 MHz
1
3
7 MHz
3.5 MHz
16 MHz
1
3
8 MHz
4 MHz
24 MHz
2
3
8 MHz
6 MHz
32 MHz
3
4
8 MHz
6.4 MHz
8.2.3.6
Wait State and Cache Hit
The FRAM controller A (FRCTL_A) has a cache that contains four 64-bit lines. The cache keeps up to 32
bytes (4 × 64 bit) from the latest accesses to FRAM. When a read is requested, the FRAM controller A
(FRCTL_A) first determines if the requested data is in the cache. If a match is found (a cache hit), then
the data is read from the cache and no physical FRAM memory access occurs. In this case, no wait state
is required and the data is accessed at the full system bus speed. If no match is found (no cache hit), then
the data is read from FRAM memory and the new data replaces one of the four 64-bit lines in the cache.
8.2.3.7
Wait State in Debug Mode
When the device is in debug mode, no wait state is applied. The NWAITS[3:0] has no influence in debug
mod. In debug mode (for example, during JTAG access to FRAM), the device system clock is controlled
externally and can be stopped at any time, thus FRAM access needs to be completed without wait state
cycles. The running speed of the CPU and DMA never exceeds the maximum FRAM access speed limit in
debug mode.