FRCTL_A Registers
304
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
FRAM Controller A (FRCTL_A)
8.6
FRCTL_A Registers
lists the memory-mapped registers for the FRCTL_A. All register offset addresses not listed in
should be considered as reserved locations and the register contents should not be modified.
The password defined in the FRCTL0 register controls access to all FRAM Controller A registers. When
the correct password is written, write access to the registers is enabled. The write access is disabled by
writing a wrong password in byte mode to FRCTL0 upper byte. Word accesses to FRCTL0 with a wrong
password triggers a PUC. A write access to a register other than FRCTL0 while write access is not
enabled causes a PUC.
Note 1:
The correct password (A5h) is written to the FRCTLPW bits by the bootcode during the device
boot-up process; therefore, the FRCTL0 (low byte), GCCTL0, and GCCTL1 registers are unlocked after
the device is powered up or reset (BOR) or after LPMx.5 wakeup.
Note 2:
All registers have word or byte register access. For a generic register ANYREG, the suffix "_L"
(ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H" (ANYREG_H)
refers to the upper byte of the register (bits 8 through 15).
Table 8-3. FRCTL_A Registers
Offset
Acronym
Register Name
Type
Reset
Section
0h
FRCTL0
FRAM Controller A Control Register 0
Read-Write
9600h
4h
GCCTL0
General Control Register 0
Read-Write
4h
6h
GCCTL1
General Control Register 1
Read-Write
0h