MemoryMap Registers
105
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Clock System (CS) Module
3.3.2 CTL1 Register (Offset = 2h) [reset = Ch]
CTL1 is shown in
and described in
.
Return to the
Clock System Control 1 Register
Figure 3-6. CTL1 Register
15
14
13
12
11
10
9
8
RESERVED
R-0h
7
6
5
4
3
2
1
0
RESERVED
DCORSEL
RESERVED
DCOFSEL
RESERVED
R-0h
R/W-0h
R-0h
R/W-6h
R-0h
Table 3-5. CTL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-7
RESERVED
R
0h
Reserved. Always reads as 0.
6
DCORSEL
R/W
0h
DCO range select. For high speed devices, this bit can be written by
the user. For low speed devices, it is always reset. See description
of DCOFSEL bit for details.
5-4
RESERVED
R
0h
Reserved. Always reads as 0.
3-1
DCOFSEL
R/W
6h
DCO frequency select. Selects frequency settings for the DCO.
Values shown below are approximate. Please refer to the device
specific datasheet.
0h (R/W) = If DCORSEL = 0: 1 MHz; If DCORSEL = 1: 1 MHz
1h (R/W) = If DCORSEL = 0: 2.67 MHz; If DCORSEL = 1: 5.33
MHz
2h (R/W) = If DCORSEL = 0: 3.5 MHz; If DCORSEL = 1: 7 MHz
3h (R/W) = If DCORSEL = 0: 4 MHz; If DCORSEL = 1: 8 MHz
4h (R/W) = If DCORSEL = 0: 5.33 MHz; If DCORSEL = 1: 16 MHz
5h (R/W) = If DCORSEL = 0: 7 MHz; If DCORSEL = 1: 21 MHz
6h (R/W) = If DCORSEL = 0: 8 MHz; If DCORSEL = 1: 24 MHz
7h (R/W) = If DCORSEL = 0: Reserved. Defaults to 8. It is not
recommended to use this setting; If DCORSEL = 1: Reserved.
Defaults to 24. It is not recommended to use this setting
0
RESERVED
R
0h
Reserved. Always reads as 0.