MemoryMap Registers
111
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Clock System (CS) Module
3.3.7 CTL6 Register (Offset = Ch) [reset = 7h]
CTL6 is shown in
and described in
.
Return to the
Clock System Control 6 Register
Figure 3-11. CTL6 Register
15
14
13
12
11
10
9
8
RESERVED
R-0h
7
6
5
4
3
2
1
0
RESERVED
MODCLKREQE
N
SMCLKREQEN
MCLKREQEN
ACLKREQEN
R-0h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
Table 3-10. CTL6 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-4
RESERVED
R
0h
Reserved. Always reads as 0.
3
MODCLKREQEN
R/W
0h
MODCLK clock request enable. Setting this enables conditional
module requests for MODCLK.
0h (R/W) = DISABLE : MODCLK conditional requests are disabled
1h (R/W) = ENABLE : MODCLK conditional requests are enabled
2
SMCLKREQEN
R/W
1h
SMCLK clock request enable. Setting this enables conditional
module requests for SMCLK.
0h (R/W) = DISABLE : SMCLK conditional requests are disabled
1h (R/W) = ENABLE : SMCLK conditional requests are enabled
1
MCLKREQEN
R/W
1h
MCLK clock request enable. Setting this enables conditional module
requests for MCLK.
0h (R/W) = DISABLE : MCLK conditional requests are disabled
1h (R/W) = ENABLE : MCLK conditional requests are enabled
0
ACLKREQEN
R/W
1h
ACLK clock request enable. Setting this enables conditional module
requests for ACLK.
0h (R/W) = DISABLE : ACLK conditional requests are disabled
1h (R/W) = ENABLE : ACLK conditional requests are enabled