Instruction Set Description
167
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
CPUX
4.6.2.7
BIT
BIT[.W]
Test bits set in source word in destination word
BIT.B
Test bits set in source byte in destination byte
Syntax
BIT src,dst
or
BIT.W src,dst
BIT.B src,dst
Operation
src .and. dst
Description
The source operand and the destination operand are logically ANDed. The result affects
only the status bits in SR.
Register mode: the register bits Rdst.19:16 (.W) resp. Rdst. 19:8 (.B) are not cleared!
Status Bits
N:
Set if result is negative (MSB = 1), reset if positive (MSB = 0)
Z:
Set if result is zero, reset otherwise
C:
Set if the result is not zero, reset otherwise. C = (.not. Z)
V:
Reset
Mode Bits
OSCOFF, CPUOFF, and GIE are not affected.
Example
Test if 1 (or both) of bits 15 and 14 of R5 (16-bit data) is set. Jump to label TONI if this is
the case. R5.19:16 are not affected.
BIT
#C000h,R5
; Test R5.15:14 bits
JNZ
TONI
; At least 1 bit is set in R5
...
; Both bits are reset
Example
A table word pointed to by R5 (20-bit address) is used to test bits in R7. Jump to label
TONI if at least 1 bit is set. R7.19:16 are not affected.
BIT.W
@R5,R7
; Test bits in R7
JC
TONI
; At least 1 bit is set
...
; Both are reset
Example
A table byte pointed to by R5 (20-bit address) is used to test bits in output Port1. Jump
to label TONI if no bit is set. The next table byte is addressed.
BIT.B
@R5+,&P1OUT
; Test I/O port P1 bits. R5 + 1
JNC
TONI
; No corresponding bit is set
...
; At least 1 bit is set