224
D90
PLUS
LINE DISTANCE PROTECTION SYSTEM – INSTRUCTION MANUAL
GROUPED PROTECTION ELEMENTS
CHAPTER 7: PROTECTION
A line compensating capacitor is a bank of three physical capacitors and their overvoltage
protecting devices (air gaps, MOVs, or both). If none of the MOV or gaps conducts any
significant current, the positive-sequence, negative-sequence, and zero-sequence
reactance of the three-phase bank equal the reactance of the actual (phase) capacitors.
However, under asymmetrical conditions such as a single-line-to-ground fault, when only
one MOV or gap may operate, the series capacitor bank would create extra (series)
asymmetry in addition to the fault (shunt) asymmetry. The positive-sequence, negative-
sequence, and zero-sequence impedances will differ from each other and will not equal
the impedance of the phase capacitors. Moreover, there may be mutual coupling between
the sequence networks representing the series capacitor bank. This makes analytical
analysis of fault conditions very burdensome. For setting calculations, however, it is
justified to assume the zero-sequence, positive-sequence, and negative-sequence
reactance of the capacitor bank equal the reactance of the actual (phase) capacitors. This
represents a worst-case low-current fault scenario, when the steady-state effects of series
compensation are most weighty.
Distance setting guidelines for protecting series compensated lines
Traditionally, the reach setting of an underreaching distance function is specified based on
the net inductive impedance between the potential source of the relay and the far-end
busbar, or location for which the zone must not overreach. Faults behind series capacitors
on the protected and adjacent lines need to be considered for this purpose. For further
illustration a sample system shown in the figure below is considered.
Figure 196: Sample series compensated system
Assuming 20% security margin, the underreaching zone shall be set as follows. At the
sending bus, one must consider an external fault at F1, as the 5
Ω
capacitor would
contribute to the overreaching effect. Any fault behind F1 is less severe as extra inductive
line impedance increases the apparent impedance.
•
Reach setting: 0.8 × (10 – 3 – 5) = 1.6
Ω
if the line-side (B) VTs are used.
•
Reach setting: 0.8 × (10 – 4 – 3 – 5) = –1.6
Ω
if the bus-side (A) VTs are used.
The negative value means that an underreaching zone cannot be used as the circuit
between the potential source of the relay and an external fault for which the relay must
not pickup, since it is overcompensated (that is, capacitive).
At the receiving bus, one must consider a fault at F2.
•
Reach setting: 0.8 × (10 – 4 – 2) = 3.2
Ω
if the line-side (B) VTs are used.
•
Reach setting: 0.8 × (10 – 4 – 3 – 2) = 0.8
Ω
if the bus-side (A) VTs are used.
However, to practically cope with the effect of sub-synchronous oscillations, it may be
necessary to reduce the reach even more. Since the characteristics of sub-synchronous
oscillations are in complex relations with fault and system parameters, no specific setting
recommendations are given with respect to extra security margin for sub-synchronous
oscillations. It is strongly recommended to use a power system simulator to verify the
reach settings or to use an adaptive D90
Plus
feature for dynamic reach control.
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