Register 18: Priority Mask Register (PRIMASK)
The
PRIMASK
register prevents activation of all exceptions with programmable priority. Reset,
non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions
should be disabled when they might impact the timing of critical tasks. This register is only accessible
in privileged mode. The
MSR
and
MRS
instructions are used to access the
PRIMASK
register, and
the
CPS
instruction may be used to change the value of the
PRIMASK
register. See the Cortex™-M4
instruction set chapter in the
ARM® Cortex™-M4 Devices Generic User Guide (literature number
)
for more information on these instructions. For more information on exception
priority levels, see “Exception Types” on page 114.
Priority Mask Register (PRIMASK)
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PRIMASK
reserved
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000
RO
reserved
31:1
Priority Mask
Description
Value
Prevents the activation of all exceptions with configurable
priority.
1
No effect.
0
0
RW
PRIMASK
0
June 18, 2014
96
Texas Instruments-Production Data
The Cortex-M4F Processor