Giga-tronics 8650B Series, Руководство по эксплуатации

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Series 8650B Universal Power Meters
3-132 Publication 31470-001, Rev C, November 2, 2017
3.19.13.1 Status Byte Register
The Status Byte Register is the primary status reporting register in the status reporting hierarchy of the 8650B.
The Status Byte Register is an 8-bit register that represents a summary of other registers such as the Event
Status Register, the Operation Status Register, and the Output Buffer. See Table 3-19 for a bit-by-bit explaination
of the Status Byte Register.
The bits in the Status Byte Register are latched meaning once a bit is set, clearing the condition does not clear
the bit. Performing the *STB? query clears the bits in the Status Byte Register. The exception is that the RQS bit
is not cleared. In this case, the entire register can be cleared by sending the Clear Status (*CLS or CS) command.
Sending *RST does not clear the register.
The Status Byte Register is ultimately used to generate a Service Request when the RQS bit (bit 6) is set. A
Service Request, SRQ, is a mechanism that enables the 8650B to asynchronously notify the host computer or
controller that certain events or conditions have occurred.
The Status Byte Register has an associated enable register. The Service Request Enable Register (SRE) is
effectively the enable mask of the Status Byte Register. The Service Request Enable Register controls which bits
in the Status Byte Register set the RQS bit (bit 6). The Request Service bit, RQS, will in turn assert a Service
Request, SRQ. A Service Request is generated anytime bit 6 (RQS) of the Status Byte Register is set high.
Table 3-19: IEEE 488.2 Status Byte Register
Bit Weight Description Set Condition
0 1 Data Ready Set when measurement data is ready.
1 2 Cal/Zero Complete Set when a Cal/Zero sequence is complete.
2 4 Entry Error Set when any number of defined entry errors has occurred.
3 8 Measurement or
Cal/Zero Error
Set when a measurement error has occurred or a Cal/Zero
error has occurred. Read the Status Message for details.
4 16 Message Available, MAV bit Set when a message is available in the output queue buffer.
5 32 Event Status Set when if any of the bits of the ESR are set provided they
are enabled by the corresponding bit of the ESE register.
6 64 Request Service, RQS bit Set when if any of the bits of the STB are set provided they
are enabled by the corresponding bit of the SRE register. A
Service Request is generated when this bit is set.
7 128 Over/Under Limit Set when Limit checking is enabled and a current
measurement is out of limit.
*STB?
Syntax: *STB?
Example:
*STB? ! QUERIES THE STATUS BYTE REGISTER VALUE
Description: This query returns the current Status Byte Register value. The response to the query is a
decimal value that corresponds to the binary-weighted sum of all the bits in the register. Values
returned by this query range from 0 through 255.
The bits in the Status Byte Register are latched meaning once a bit is set, clearing the
condition does not clear the bit. Performing the *STB? query clears the bits in the Status Byte
Register.. The entire register can be cleared by sending the Clear Status (*CLS or CS)
command.