Rohde & Schwarz 1065.6000.20, Operating Manual

Page: 413 / 438

Contents - Maintenance and Instrument Interfaces FSE
1065.6016.12 8.20 E-15
RSDLLWaitSrq
The function waits until the instrument triggers an SRQ with the handle
ud
.
VB format:
Function RSDLLWaitSrq (ByVal ud%, Result%, ibsta%, iberr%,
ibcntl&) As Integer
C format:
void FAR PASCAL RSDLLWaitSrq( short ud, short far *result,
short far *ibsta, short far *iberr, unsigned long far *ibcntl)
C format (Unix):
short RSDLLWaitSrq( short ud, short *result, short *ibsta,
short *iberr, unsigned long *ibcntl)
Parameter:
ud
Device handle
result
Reference to an integer value in which the library
returns the status of the SRQ bit.
0 - no SRQ occurred within the timeout
1 - SRQ occurred within the timeout
Parameter:
RSDLLWaitSrq( ud, result, ibsta, iberr, ibcntl );
The function waits until one of the two following events occurs:
•
The instrument triggers an SRQ.
•
No SRQ occurs during the timeout defined with
RSDLLibtmo().
RSDLLSwapBytes
This function changes the display of binary numbers on non-Intel platforms (only with Windows NT
controller)..
VB format: Not provided at present since it is required only on non-Intel platforms.
C format:
void FAR PASCAL RSDLLSwapBytes( void far *pArray, const long
size, const long count)
C format (Unix):
void RSDLLSwapBytes( void *pArray, const long size, const long
count)
Parameter:
pArray
Array in which modifications are made
size
Size of a single element in
pArray
count
Number of elements in
pArray
Example:
RSDLLSwapBytes( Buffer, sizeof(float), ibcntl/sizeof(float))
This function swaps the display of various elements from Big Endian to Little Endian and vice versa. It is
expected that a coherent storage area of elements of the same file type (
size
byte) is transferred to
pArray
. This function has no effect on Intel platforms.
Different types of processor architecture store data in different byte sequences. For example, Intel
processors store data in the reverse order of Motorola processors. Comparison of byte sequences:
Byte sequence Use in Display in memory Description
Big Endian Motorola processors,
network standard Most significant byte at
least significant address The most significant byte is at the left end
of the word.
Little Endian Intel processors Least significant byte at
least significant address The most significant byte is at the right
end of the word.