559
32072H–AVR32–10/2012
AT32UC3A3
This gives a maximum baud rate of CLK_USART divided by 8, assuming that CLK_USART is
the fastest clock available, and that MR.OVER is one.
25.6.4.2
Baud Rate Calculation Example
shows calculations based on the CD field to obtain 38400 baud from different source
clock frequencies. This table also shows the actual resulting baud rate and error.
The baud rate is calculated with the following formula (MR.OVER=0):
The baud rate error is calculated with the following formula. It is not recommended to work with
an error higher than 5%.
25.6.4.3
Fractional Baud Rate in Asynchronous Mode
The baud rate generator has a limitation: the source frequency is always a multiple of the baud
rate. An approach to this problem is to integrate a high resolution fractional N clock generator,
outputting fractional multiples of the reference source clock. This fractional part is selected with
Table 25-7.
Baud Rate Example (OVER=0)
Source Clock (Hz)
Expected Baud
Rate (bit/s)
Calculation Result
CD
Actual Baud Rate (bit/s)
Error
3 686 400
38 400
6.00
6
38 400.00
0.00%
4 915 200
38 400
8.00
8
38 400.00
0.00%
5 000 000
38 400
8.14
8
39 062.50
1.70%
7 372 800
38 400
12.00
12
38 400.00
0.00%
8 000 000
38 400
13.02
13
38 461.54
0.16%
12 000 000
38 400
19.53
20
37 500.00
2.40%
12 288 000
38 400
20.00
20
38 400.00
0.00%
14 318 180
38 400
23.30
23
38 908.10
1.31%
14 745 600
38 400
24.00
24
38 400.00
0.00%
18 432 000
38 400
30.00
30
38 400.00
0.00%
24 000 000
38 400
39.06
39
38 461.54
0.16%
24 576 000
38 400
40.00
40
38 400.00
0.00%
25 000 000
38 400
40.69
40
38 109.76
0.76%
32 000 000
38 400
52.08
52
38 461.54
0.16%
32 768 000
38 400
53.33
53
38 641.51
0.63%
33 000 000
38 400
53.71
54
38 194.44
0.54%
40 000 000
38 400
65.10
65
38 461.54
0.16%
50 000 000
38 400
81.38
81
38 580.25
0.47%
60 000 000
38 400
97.66
98
38 265.31
0.35%
BaudRate
CLK
_
USART
CD
16
⋅
-----------------------------------
=
Error
1
ExpectedBaudRate
ActualBaudRate
---------------------------------------------------
⎝
⎠
⎛
⎞
–
=
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
