107
32072H–AVR32–10/2012
AT32UC3A3
11. External Interrupt Controller (EIC)
Rev: 2.4.0.0
11.1
Features
•
Dedicated interrupt request for each interrupt
•
Individually maskable interrupts
•
Interrupt on rising or falling edge
•
Interrupt on high or low level
•
Asynchronous interrupts for sleep modes without clock
•
Filtering of interrupt lines
•
Maskable NMI interrupt
•
Keypad scan support
11.2
Overview
The External Interrupt Controller (EIC) allows pins to be configured as external interrupts. Each
external interrupt has its own interrupt request and can be individually masked. Each external
interrupt can generate an interrupt on rising or falling edge, or high or low level. Every interrupt
input has a configurable filter to remove spikes from the interrupt source. Every interrupt pin can
also be configured to be asynchronous in order to wake up the part from sleep modes where the
CLK_SYNC clock has been disabled.
A Non-Maskable Interrupt (NMI) is also supported. This has the same properties as the other
external interrupts, but is connected to the NMI request of the CPU, enabling it to interrupt any
other interrupt mode.
The EIC can wake up the part from sleep modes without triggering an interrupt. In this mode,
code execution starts from the instruction following the sleep instruction.
The External Interrupt Controller has support for keypad scanning for keypads laid out in rows
and columns. Columns are driven by a separate set of scanning outputs, while rows are sensed
by the external interrupt lines. The pressed key will trigger an interrupt, which can be identified
through the user registers of the module.
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
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Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...