386
32072H–AVR32–10/2012
AT32UC3A3
20.6
User Interface
The GPIO controls all the I/O pins on the AVR32 microcontroller. The pins are managed as 32-
bit ports that are configurable through a PB interface. Each port has a set of configuration regis-
ters. The overall memory map of the GPIO is shown below. The number of pins and hence the
number of ports are product specific.
Figure 20-6. Overall Mermory Map
In the GPIO Controller Function Multiplexingtable in the Package and Pinout chapter, each
GPIO line has a unique number. Note that the PA, PB, PC and PX ports do not directly corre-
spond to the GPIO ports. To find the corresponding port and pin the following formula can be
used:
GPIO port = floor((GPIO number) / 32), example: floor((36)/32) = 1
GPIO pin = GPIO number mod 32, example: 36 mod 32 = 4
The table below shows the configuration registers for one port. Addresses shown are relative to
the port address offset. The specific address of a configuration register is found by adding the
Port 0 Configuration Registers
Port 1 Configuration Registers
Port 2 Configuration Registers
Port 3 Configuration Registers
Port 4 Configuration Registers
0x0000
0x0100
0x0200
0x0300
0x0400
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
