Atmel AT32UC3A3128, Manual

Page: 197 / 1021

197
32072H–AVR32–10/2012
AT32UC3A3
•Slow clock mode transition
A reload configuration wait state is also inserted when the slow clock mode is entered or exited,
after the end of the current transfer (see
Section 15.6.8 ).
15.6.5.4 Read to write wait state
Due to an internal mechanism, a wait cycle is always inserted between consecutive read and
write SMC accesses.
This wait cycle is referred to as a read to write wait state in this document.
This wait cycle is applied in addition to chip select and reload user configuration wait states
when they are to be inserted. See
Figure 15-15 on page 193 .
15.6.6 Data Float Wait States
Some memory devices are slow to release the external bus. For such devices, it is necessary to
add wait states (data float wait states) after a read access:
• before starting a read access to a different external memory.
• before starting a write access to the same device or to a different external one.
The Data Float Output Time (t
DF
) for each external memory device is programmed in the Data
Float Time field of the MODE register (MODE.TDFCYCLES) for the corresponding chip select.
The value of MODE.TDFCYCLES indicates the number of data float wait cycles (between 0 and
15) before the external device releases the bus, and represents the time allowed for the data
output to go to high impedance after the memory is disabled.
Data float wait states do not delay internal memory accesses. Hence, a single access to an
external memory with long t
DF
will not slow down the execution of a program from internal
memory.
The data float wait states management depends on the MODE.READMODE bit and the TDF
Optimization bit of the MODE register (MODE.TDFMODE) for the corresponding chip select.
15.6.6.1 Read mode
Writing a one to the MODE.READMODE bit indicates to the SMC that the NRD signal is respon-
sible for turning off the tri-state buffers of the external memory device. The data float period then
begins after the rising edge of the NRD signal and lasts MODE.TDFCYCLES cycles of the
CLK_SMC clock.
When the read operation is controlled by the NCS signal (MODE.READMODE = 0), the
MODE.TDFCYCLES field gives the number of CLK_SMC cycles during which the data bus
remains busy after the rising edge of NCS.
Figure 15-19 on page 198 illustrates the data float period in NRD-controlled mode
(MODE.READMODE =1), assuming a data float period of two cycles (MODE.TDFCYCLES = 2).
Figure 15-20 on page 198 shows the read operation when controlled by NCS (MODE.READ-
MODE = 0) and the MODE.TDFCYCLES field equals to three.