Atmel AT32UC3A3128, Manual

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32072H–AVR32–10/2012
AT32UC3A3
Figure 27-19. Example of an OUT Endpoint with one Data Bank
Figure 27-20. Example of an OUT Endpoint with two Data Banks
•Detailed description
The data is read, following the next flow:
• When the bank is full, RXOUTI and FIFOCON are set, what triggers an EPnINT interrupt if
RXOUTE is one.
• The user acknowledges the interrupt by writing a one to RXOUTIC in order to clear RXOUTI.
• The user can read the byte count of the current bank from BYCT to know how many bytes to
read, rather than polling RWALL.
• The user reads the data from the current bank by using the USBFIFOnDATA register (see
”USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA)” on page 747 ), until all the
expected data frame is read or the bank is empty (in which case RWALL is cleared and BYCT
reaches zero).
• The user frees the bank and switches to the next bank (if any) by clearing FIFOCON.
If the endpoint uses several banks, the current one can be read while the following one is being
written by the host. Then, when the user clears FIFOCON, the following bank may already be
ready and RXOUTI is set immediately.
In Hi-Speed mode, the PING and NYET protocol is handled by the USBB. For single bank, a
NYET handshake is always sent to the host (on Bulk-out transaction) to indicate that the current
packet is acknowledged but there is no room for the next one. For double bank, the USBB
OUT
DATA
(bank 0)
ACK
RXOUTI
FIFOCON
HW
OUT
DATA
(bank 0)
ACK
HW
SW
SW
SW
read data from CPU
BANK 0
read data from CPU
BANK 0
NAK
OUT
DATA
(bank 0)
ACK
RXOUTI
FIFOCON
HW
OUT
DATA
(bank 1)
ACK
SW
SW
read data from CPU
BANK 0
HW
SW
read data from CPU
BANK 1